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acpl-332j 2.5 amp output current igbt gate driver optocoupler with integrated (v ce ) desaturation detection, uvlo fault status feedback and active miller clamping data sheet features ? under voltage lock-out protection (uvlo) with hysteresis ? desaturation detection ? miller clamping ? open collector isolated fault feedback ? soft igbt turn-of ? fault reset by next led turn-on (low to high) after fault mute period ? available in so-16 package ? safety approvals: ul approved, 3750 v rms for 1 minute, csa approved, iec/en/din-en 60747-5-2 approved v iorm = 891 v peak specifcations ? 2.5 a maximum peak output current ? 2.0 a minimum peak output current ? 250 ns maximum propagation delay over temperature range ? 100 ns maximum pulse width distortion (pwd) ? 15 kv/s minimum common mode rejection (cmr) at v cm = 1500 v ? i cc(max) < 5 ma maximum supply current ? wide v cc operating range: 15 v to 30 v over temperature range ? 1.7 a miller clamp. clamp pin short to v ee if not used ? wide operating temperature range: C40c to 105c applications ? isolated igbt/power mosfet gate drive ? ac and brushless dc motor drives ? industrial inverters and uninterruptible power supply (ups) description the acpl-332j is an advanced 2.5 a output current, easy- to-use, intelligent gate driver which makes igbt v ce fault protection compact, afordable, and easy-to implement. features such as integrated v ce detection, under voltage lockout (uvlo), soft igbt turn-of, isolated open collector fault feedback and active miller clamping provide maximum design fexibility and circuit protec - tion. the acpl-332j contains a gaasp led. the led is optically coupled to an integrated circuit with a power output stage. acpl-332j is ideally suited for driving power igbts and mosfets used in motor control inverter applications. the voltage and current supplied by these optocouplers make them ideally suited for directly driving igbts with ratings up to 1200 v and 150 a. for igbts with higher ratings, the acpl-332j can be used to drive a discrete power stage which drives the igbt gate. the acpl-332j has an insulation voltage of v iorm = 891 v peak . block diagram shi el d shi el d d r i v e r v e de sa t v cc2 v ou t v cl am p v ee v cc1 v s fa ul t ano de ca th od e v cl am p v le d 6, 7 5, 8 2 3 1, 4 13 11 14 9, 1 2 10 16 15 de sa t uv lo le d1 le d2 shi el d shi el d d r i v e r v e de sa t v cc2 v ou t v cl am p v ee v cc1 v s fa ul t ano de ca th od e v cl am p v le d 6, 7 5, 8 2 3 1, 4 13 11 14 9, 1 2 10 16 15 de sa t uv lo le d1 le d2 caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. lead (pb) free rohs 6 fully compliant rohs 6 fully compliant options available; -xxxe denotes a lead-free product
2 pin description 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e pin symbol description 1 v s input ground 2 v cc1 positive input supply voltage. (4.5 v to 5.5 v) 3 fault fault output. fault changes from a high impedance state to a logic low output within 5 s of the voltage on the desat pin exceeding an internal reference voltage of 7 v. fault output is an open collector which allows the fault outputs from all acpl-332j in a circuit to be connected together in a wired or forming a single fault bus for inter - facing directly to the micro-controller. 4 v s input ground 5 cathode cathode 6 anode anode 7 anode anode 8 cathode cathode 9 v ee output supply voltage. 10 v clamp miller clamp 11 v out gate drive voltage output 12 v ee output supply voltage. 13 v cc2 positive output supply voltage 14 desat desaturation voltage input. when the voltage on desat exceeds an internal reference voltage of 6.5 v while the igbt is on, fault output is changed from a high impedance state to a logic low state within 5 s. 15 v led led anode. this pin must be left unconnected for guaran - teed data sheet performance. (for optical coupling testing only) 16 v e common (igbt emitter) output supply voltage. ordering information acpl-332j is ul recognized with 3750 vrms for 1 minute per ul1577. part number option package surface mount tape& reel iec/en/din en 60747-5-2 quantity rohs compliant acpl-332j -000e so-16 x x 45 per tube -500e x x x 850 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: ACPL-332J-500E to order product of so-16 surface mount package in tape and reel packaging with iec/en/din en 60747-5-2 safety approval in rohs compliant. example 2: acpl-332j-000e to order product of so-16 surface mount package in tube packaging with iec/en/din en 60747-5- 2 safety approval and rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information. remarks: the notation #xxx is used for existing products, while (new) products launched since 15th july 2001 and rohs compliant option will use -xxxe.
3 package outline drawings acpl-332j 16-lead surface mount package dimensions in inches (millimeters) notes: initial and continued variation in the color of the acpl-332js white mold compound is normal and does note afect device performance or reliability. floating lead protrusion is 0.25 mm (10 mils) max. 9 0.295 0.010 (7.493 0.254) 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 0.018 (0.457) 0.138 0.005 (3.505 0.127) 9 0.406 0.10 (10.312 0.254) 0.408 0.010 (10.363 0.254) 0.025 min . 0.008 0.003 (0.203 0.076) standoff 0.345 0.010 (8.763 0.254) 0 - 8 0.018 (0.457) 0.050 (1.270) all leads to be coplanar 0.002 a 332j yyww type number date code 0.458 (11.63) 0.085 (2.16) 0.025 (0.64) land pattern recommendation
4 solder refow thermal profle recommended pb-free ir profle note: non-halide fux should be used. 0 time (seconds) temperature ( c) 200 100 50 150 100 200 250 300 0 30 sec. 50 sec. 30 sec. 160 c 140 c 150 c peak temp. 245 c peak temp. 240 c peak temp. 230 c soldering tim e 200 c preheating tim e 150 c, 90 + 30 sec. 2.5 c 0.5 c/sec. 3 c + 1 c/ - 0.5 c tight typical loose room temperature preheating rate 3 c + 1 c/ - 0.5 c/sec. reflow heating rate 2.5 c 0.5 c/sec. 217 c ramp-dow n 6 c/sec. max. ramp-up 3 c/sec. max. 150 - 200 c 260 +0/-5 c t 25 c to peak 60 to 150 sec. 20-40 sec. time within 5 c of actual peak temperature t p t s preheat 60 to 180 sec. t l t l t smax t smin 25 t p time temperature no tes: the time from 25 c to peak temperature = 8 minutes max. t smax = 200 c, t smin = 150 c note: non-halide fux should be used.
5 table 1. iec/en/din en 60747-5-2 insulation characteristics* description symbol characteristic unit installation classifcation per din vde 0110/1.89, table 1 for rated mains voltage 150 v rms for rated mains voltage 300 v rms for rated mains voltage 600 v rms i C iv i C iv i C iii climatic classifcation 55/100/21 pollution degree (din vde 0110/1.89) 2 maximum working insulation voltage v iorm 891 v peak input to output test voltage, method b**, v iorm x 1.875=v pr , 100% production test with t m =1 sec, partial discharge < 5 pc v pr 1670 v peak input to output test voltage, method a**, v iorm x 1.5=v pr , type and sample test, t m =60 sec, partial discharge < 5 pc v pr 1336 v peak highest allowable overvoltage (transient overvoltage t ini = 10 sec) v iotm 6000 v peak safety-limiting values C maximum values allowed in the event of a failure. case temperature t s 175 c input current i s, input 400 ma output power p s, output 1200 mw insulation resistance at t s , v io = 500 v r s >10 9 w * isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. surface mount classifcation is class a in accordance with ceccoo802. ** refer to the optocoupler section of the isolation and control components designers catalog, under product safety regulations section iec/en/ din en 60747-5-2, for a detailed description of method a and method b partial discharge test profles. dependence of safety limiting values on temperature. (take from ds av01-0579en pg.7) regulatory information the acpl-332j is approved by the following organizations: iec/en/din en 60747-5-2 approval under: iec 60747-5-2 :1997 + a1:2002 en 60747-5-2:2001 + a1:2002 din en 60747-5-2 (vde 0884 teil 2):2003-01 ul approval under ul 1577, component recognition program up to v iso = 3750 v rms . file e55361. csa approval under csa component acceptance notice #5, file ca 88324.
6 table 2. insulation and safety related specifcations parameter symbol acpl-332j units conditions minimum external air gap (clearance) l(101) 8.3 mm measured from input terminals to output terminals, shortest distance through air. minimum external tracking (creepage) l(102) 8.3 mm measured from input terminals to output terminals, shortest distance path along body. minimum internal plastic gap (internal clearance) 0.5 mm through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1) table 3. absolute maximum ratings parameter symbol min. max. units note storage temperature t s -55 125 c operating temperature t a -40 105 c 2 output ic junction temperature t j 125 c 2 average input current i f(avg) 25 ma 1 peak transient input current, (<1 s pulse width, 300pps) i f(tran) 1.0 a reverse input voltage v r 5 v high peak output current i oh(peak) 2.5 a 3 low peak output current i ol(peak) 2.5 a 3 positive input supply voltage v cc1 -0.5 5.5 v fault output current i fault 8.0 ma fault pin voltage v fault -0.5 v cc1 v total output supply voltage (v cc2 - v ee ) -0.5 33 v negative output supply voltage (v e - v ee ) -0.5 15 v 6 positive output supply voltage (v cc2 - v e ) -0.5 33 - (v e - v ee ) v gate drive output voltage v o(peak) -0.5 v cc2 v peak clamping sinking current i clamp 1.7 a miller clamping pin voltage v clamp -0.5 v cc2 v desat voltage v desat v e v e + 10 v output ic power dissipation p o 600 mw 2 input ic power dissipation p i 150 mw 2 solder refow temperature profle see package outline drawings section table 4. recommended operating conditions parameter symbol min. max. units note operating temperature t a - 40 105 c 2 total output supply voltage (v cc2 - v ee ) 15 30 v 7 negative output supply voltage (v e - v ee ) 0 15 v 4 positive output supply voltage (v cc2 - v e ) 15 30 - (v e - v ee ) v input current (on) i f(on) 8 12 ma input voltage (off) v f(off) - 3.6 0.8 v
7 table 5. electrical specifcations (dc) unless otherwise noted, all typical values at t a = 25c, v cc2 - v ee = 30 v, v e - v ee = 0 v; all minimum/maximum specifcations are at recommended operating conditions. positive supply voltage used. parameter symbol min. typ. max. units test conditions fig. note fault logic low output voltage v faultl 0.1 0.4 v i fault = 1.1 ma, v cc1 = 5.5v 0.1 0.4 v i fault = 1.1 ma, v cc1 = 3.3v fault logic high output current i faulth 0.02 0.5 a v fault = 5.5 v, v cc1 = 5.5v 0.002 0.3 a v fault = 3.3 v, v cc1 = 3.3v high level output current i oh -0.5 -1.5 a v o = v cc2 - 4 2, 4, 21 5 -2.0 a v o = v cc2 C 15 3 low level output current i ol 0.5 1.5 a v o = v ee + 2.5 3, 5, 22 5 2.0 a v o = v ee + 15 3 low level output current during fault condition i olf 90 140 230 ma v out - v ee = 14 v 6 high level output voltage v oh v cc -2.9 v cc -2.0 v i o = -650 a 4, 6, 23 7, 8, 9 23 low level output voltage v ol 0.17 0.5 v i o = 100 ma 5, 7, 24 clamp pin threshold voltage v tclamp 2.0 v clamp low level sinking current i cl 0.35 1.1 a v o = v ee + 2.5 8 high level supply current i cc2h 2.5 5 ma i o = 0 ma 9, 10, 25, 26 9 low level supply current i cc2l 2.5 5 ma i o = 0 ma blanking capacitor charging current i chg -0.13 -0.24 -0.33 ma v desat = 2 v 11, 27 9, 10 blanking capacitor discharge current i dschg 10 30 ma v desat = 7.0 v 28 desat threshold v desat 6 6.5 7.5 v v cc2 -v e >v uvlo- 12 9 uvlo threshold v uvlo+ 10.5 11.6 12.5 v v o > 5 v 7, 9, 11 v uvlo- 9.2 10.3 11.1 v v o < 5 v 7, 9, 12 uvlo hysteresis (v uvlo+ - v uvlo- ) 0.4 1.3 v threshold input current low to high i flh 2.0 8 ma i o = 0 ma, v o > 5 v threshold input voltage high to low v fhl 0.8 v input forward voltage v f 1.2 1.6 1.95 v i f = 10 ma temperature coefcient of input forward voltage d v f / d t a -1.3 mv/c input reverse breakdown voltage bv r 5 v i r = 10 m a input capacitance c in 70 pf f = 1 mhz, v f = 0 v
8 table 6. switching specifcations (ac) unless otherwise noted, all typical values at t a = 25c, v cc2 - v ee = 30 v, v e - v ee = 0 v; all minimum/maximum specifcations are at recommended operating conditions. only positive supply voltage used. parameter symbol min. typ. max. units test conditions fig. note propagation delay time to high output level t plh 100 180 250 ns r g = 10 w , c g = 10 nf, f = 10 khz, duty cycle = 50%, i f = 10 ma, v cc2 = 30 v 1, 13, 14, 15, 16, 29 13, 15 propagation delay time to low output level t phl 100 180 250 ns 1, 13, 14, 15, 16, 29 pulse width distortion pwd -100 20 100 ns 14, 17 propagation delay diference between any two parts or channels (t phl - t plh ) pdd -350 350 ns 17, 16 rise time t r 50 ns fall time t f 50 ns desat sense to 90%vo delay t desat(90%) 0.15 0.5 s c desat = 100pf, r g = 10 w , c g = 10 nf, v cc2 = 30 v 17, 30, 37 19 desat sense to 10% vo delay t desat(10%) 2 3 s c desat = 100pf, r g = 10 w , c g = 10 nf, v cc2 = 30 v 18, 19, 20, 30, 37 desat sense to low level fault signal delay t desat(fault) 0.25 0.5 s c desat = 100pf, r f = 2.1 k w , r g = 10 w , c g = 10 nf, v cc2 = 30 v 30, 37 18 desat sense to desat low propagation delay t desat(low) 0.25 s c desat = 100pf, r f = 2.1 k w , r g = 10 w , c g = 10 nf, v cc2 = 30 v 30, 37 19 desat input mute t desat(mute) 5 s 37 20 reset to high level fault signal delay t reset(fault) 0.3 1 2.0 s c desat = 100pf, rf = 2.1 k w , rg = 10 w , cg = 10 nf, v cc1 = 5.5v, v cc2 = 30 v 0.8 1.5 2.5 s c desat = 100pf, r f = 2.1 k w , rg = 10 w , cg = 10 nf, v cc1 = 3.3v, v cc2 = 30 v output high level common mode transient immunity |cm h | 15 25 kv/s t a = 25c, i f = 10 ma v cm = 1500 v, v cc2 = 30 v 31, 32, 33, 34 21 output low level common mode transient immunity |cm l | 15 25 kv/s t a = 25c, v f = 0 v v cm = 1500 v, v cc2 = 30 v 31, 32, 33, 34 22
9 table 7. package characteristics parameter symbol min. typ. max. units test conditions fig. note input-output momentary withstand voltage v iso 3750 v rms rh < 50%, t = 1 min., t a = 25c 6, 7 input-output resistance r i-o > 10 9 w v i-o = 500 v 7 input-output capacitance c i-o 1.3 pf freq=1 mhz output ic-to-pins 9 &10 thermal resistance q 09-10 30 c/w t a = 25c notes: 1. derate linearly above 70c free air temperature at a rate of 0.3 ma/c. 2. in order to achieve the absolute maximum power dissipation specifed, pins 4, 9, and 10 require ground plane connections and may require airfow. see the thermal model section in the application notes at the end of this data sheet for details on how to estimate junction temperature and power dissipation. in most cases the absolute maximum output ic junction temperature is the limiting factor. the actual power dissipation achievable will depend on the application environment (pcb layout, air fow, part placement, etc.). see the recommended pcb layout section in the application notes for layout considerations. output ic power dissipation is derated linearly at 10 mw/c above 90c. input ic power dissipation does not require derating. 3. maximum pulse width = 10 s. this value is intended to allow for component tolerances for designs with i o peak minimum = 2.0 a. derate linearly from 3.0 a at +25c to 2.5 a at +105c. this compensates for increased i opeak due to changes in v ol over temperature. 4. this supply is optional. required only when negative gate drive is implemented. 5. maximum pulse width = 50 s. 6. see the slow igbt gate discharge during fault condition section in the applications notes at the end of this data sheet for further details. 7. 15 v is the recommended minimum operating positive supply voltage (v cc2 - v e ) to ensure adequate margin in excess of the maximum v uvlo+ threshold of 12.5v. for high level output voltage testing, v oh is measured with a dc load current. when driving capacitive loads, v oh will approach v cc as i oh approaches zero units. 8. maximum pulse width = 1.0 ms. 9. once v o of the acpl-332j is allowed to go high (v cc2 - v e > v uvlo ), the desat detection feature of the acpl-332j will be the primary source of igbt protection. uvlo is needed to ensure desat is functional. once v uvlo+ > 12.5 v, desat will remain functional until v uvlo- < 9.2 v. thus, the desat detection and uvlo features of the acpl-332j work in conjunction to ensure constant igbt protection. 10. see the desat fault detection blanking time section in the applications notes at the end of this data sheet for further details. 11. this is the increasing (i.e. turn-on or positive going direction) of v cc2 - v e 12. this is the decreasing (i.e. turn-of or negative going direction) of v cc2 - v e 13. this load condition approximates the gate load of a 1200 v/150a igbt. 14. pulse width distortion (pwd) is defned as |t phl - t plh | for any given unit. 15. as measured from i f to v o . 16. the diference between t phl and t plh between any two acpl-332j parts under the same test conditions. 17. as measured from anode, cathode of led to v out 18. this is the amount of time from when the desat threshold is exceeded, until the fault output goes low. 19. this is the amount of time the desat threshold must be exceeded before v out begins to go low, and the fault output to go low. this is supply voltage dependent. 20. auto reset: this is the amount of time when v out will be asserted low after desat threshold is exceeded. see the description of operation (auto reset) topic in the application information section. 21. common mode transient immunity in the high state is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in the high state (i.e., v o > 15 v or fault > 2 v). a 100 pf and a 2.1 k? pull-up resistor is needed in fault detection mode. 22. common mode transient immunity in the low state is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in a low state (i.e., v o < 1.0 v or fault < 0.8 v). 23. to clamp the output voltage at v cc - 3 v be , a pull-down resistor between the output and v ee is recommended to sink a static current of 650 a while the output is high. see the output pull-down resistor section in the application notes at the end of this data sheet if an output pull-down resistor is not used.
10 figure 2. i oh vs. temperature figure 3. i ol vs. temperature figure 4. v oh vs. temperature figure 5. v ol vs. temperature 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 5 t a - t e m p e r a t u r e - o c i o h - o u t p u t h i g h c u r r e n t - a 0 1 2 3 4 5 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 5 t a - t e m p e r a t u r e - o c i o l - o u t p u t l o w c u r r e n t - - - - - v o u t = v e e + 1 5 v _ _ _ v o u t = v e e + 2 . 5 v 0 0 . 0 5 0 . 1 0 . 1 5 0 . 2 0 . 2 5 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 5 t a - t e m p e r a t u r e - o c v o l - o u t p u t l o w v o l t a g e - v figure 1. vout propagation delay waveforms i f v out t phl t plh t f t r 10% 50% 90% - 2 . 5 - 2 - 1 . 5 - 1 - 0 . 5 0 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 5 i o u t = - 6 5 0 u a t a - t e m p e r a t u r e - o c ( v o h - v c c ) - h i g h o u t p u t v o l t a g e d r o p - v _ _ _ _
11 figure 8. i cl vs. temperature 0 1 2 3 4 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 5 t a - t e m p e r a t u r e - o c i c l - c l a m p l o w l e v e n s i n k i n g c u r r e n t 15 20 25 30 2.25 2.35 2.45 2.55 2.65 v cc2 - outpur supply voltage - v i cc2 - output supply current - ma ---------i cc 2 h _ ________ i cc 2 l 2 . 0 0 2 . 2 5 2 . 5 0 2 . 7 5 3 . 0 0 3 . 2 5 3 . 5 0 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 5 t a - t e m p e r a t u r e - o c i c c 2 - o u t p u t s u p p l y c u r r e n t - m a - - - - - - - - - i c c 2 h _ _ _ _ _ _ _ _ _ i c c 2 l - 0 . 3 5 - 0 . 3 0 - 0 . 2 5 - 0 . 2 0 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 5 t a - t e m p e r a t u r e - o c i c h - b l a n k i n g c a p a c i t o r c h a r g i n g c u r r e n t - m a figure 9. i cc2 vs. temperature figure 10. i cc2 vs. v cc2 figure 11. i chg vs. temperature 2 8 . 0 2 8 . 5 2 9 . 0 2 9 . 5 3 0 . 0 0 0 . 2 0 . 4 0 . 6 0 . 8 1 i o h - o u t p u t h i g h c u r r e n t - a v o h - h i g h o u t p u t v o l t a g e d r o p - v _ _ _ _ 1 0 5 o c _ _ _ _ _ _ 2 5 o c - - - - - - - - - - 4 0 o c figure 6. v oh vs. i oh figure 7. v ol vs. i ol 0 1 2 3 4 5 6 7 8 0 0 . 5 1 1 . 5 2 2 . 5 i o l - o u t p u t l o w c u r r e n t - a v o l - l o w o u t p u t v o l t a g e d r o p - v _ _ _ _ 1 0 5 o c _ _ _ _ _ _ 2 5 o c - - - - - - - - - - 4 0 o c
12 figure 14. propagation delay vs. supply voltage 100 150 200 250 300 15 20 25 30 vcc - supply voltage - v t p - propagation delay - ns ----------t plh _______t phl 100 150 200 250 300 0 1 0 2 0 3 0 4 0 5 0 load resistance - ohm t p - propagation delay - ms ----------t plh _______t phl figure 15. propagation delay vs. load resistance figure 16. propagation delay vs. load capacitance 0 100 200 300 0 1 0 2 0 3 0 4 0 5 0 load capacitance - nf ----------t plh _______t phl t p - propagation delay - ms figure 12. desat threshold vs. temperature figure 13. propagation delay vs. temperature 6 . 0 6 . 5 7 . 0 7 . 5 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 5 t a - t e m p e r a t u r e - o c v d e s a t - d e s a t t h r e s h o l d - v 1 0 0 1 5 0 2 0 0 2 5 0 3 0 0 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 5 t a - t e m p e r a t u r e - o c t p - p r o p a g a t i o n d e l a y - n s - - - - - - - - - - t p l h _ _ _ _ _ _ _ t p h l
13 figure 18. desat sense to 10% vout delay vs. temperature 1 . 0 1 . 5 2 . 0 2 . 5 3 . 0 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 5 t a - t e m p e r a t u r e - o c t d e s a t - d e s a t s e n s e t o 1 0 % v o d e l a y - u s - - - - - - - v c c 2 = 1 5 v _ _ _ _ _ v c c 2 = 3 0 v figure 19. desat sense to 10% vout delay vs. load resistance 0.0 1.0 2.0 3.0 4.0 10 20 30 40 50 load resistance - ohm -------v cc2 =15v _____v cc2 =30v t desat10% - desat sense to 10% vo delay - us 0.000 0.004 0.008 0.012 0 1 0 2 0 3 0 4 0 5 0 load capacitance - nf -------v cc2 =15v _____v cc2 =30v t desat10% - desat sense to 10% vo delay - ms figure 20. desat sense to 10% vout delay vs. load capacitance 1 0 0 1 5 0 2 0 0 2 5 0 3 0 0 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 5 t a - t e m p e r a t u r e - o c t d e s a t 9 0 % - d e s a t s e n s e t o 9 0 % v o d e l a y - n s figure 17. desat sense to 90% vout delay vs. temperature
14 figure 21. i oh pulsed test circuit figure 22. i ol pulsed test circuit figure 23. v oh pulsed test circuit 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e + _ 10 ma + _ 0. 1 f 0. 1 f 15 v pu ls ed i ou t 30 v 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 v s ca th od e ano de ano de ca th od e + _ 10 ma + _ 0. 1 f 0. 1 f 0. 1 f 0. 1 f 15 v pu ls ed i ou t 30 v 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e + _ + _ 0. 1 f 0. 1 f 15 v pu lse d i ou t 30 v + _ 0. 1 f 0. 1 f 1 2 3 4 5 6 7 8 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 v e v l e d d e s a t v c c 2 v e e v o u t v c l a m p v e e v s v c c 1 f a u l t v s c a t h o d e a n o d e a n o d e c a t h o d e + _ 0 . 1 f 0 . 1 f 6 5 0 a v o u t 3 0 v 1 0 m a 1 0 m a
15 figure 24. v ol pulsed test circuit figure 25. i cc2h test circuit figure 26. i cc2l test circuit 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e + _ 0. 1 f 0. 1 f 100m a v ou t 30 v 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e + _ 0. 1 f 0. 1 f 0. 1 f 0. 1 f 100m a v ou t 30 v 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e + _ 0. 1 f 0. 1 f i cc2 30 v 10 ma 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e + _ 0. 1 f 0. 1 f 0. 1 f 0. 1 f i cc2 30 v 10 ma 10 ma 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e + _ 0. 1 f 0. 1 f 30 v i cc2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 v s ca th od e ano de ano de ca th od e + _ 0. 1 f 0. 1 f 0. 1 f 0. 1 f 30 v i cc2
16 figure 27. i chg pulsed test circuit 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e + _ 0. 1 f 0. 1 f i chg 30 v 10 m a 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e + _ 0. 1 f 0. 1 f i chg 30 v 10 m a 10 m a figure 28. i dschg test circuit 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e + _ 0. 1 f 0. 1 f 7v 30 v + _ idschg 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e + _ 0. 1 f 0. 1 f 7v 30 v + _ idschg figure 29. t plh , t phl , t f , t r , test circuit 10 nf 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e + _ 0. 1 f 0. 1 f v ou t 30 v 10 ? 10 ma, 10khz, 50 % du ty cyc le 10 nf 10 nf 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e + _ 0. 1 f 0. 1 f v ou t 30 v 10 ma, 10khz, 50 % du ty cyc le
17 v cm 10 10 nf 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e 0. 1 f sco pe 30 v 43 0 ? 2. 1k ? 0. 1 f 15 pf 5v v cm 10 ? 10 nf 10 nf 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e 0. 1 f 0. 1 f sco pe 30 v 0. 1 f 0. 1 f 15 pf 15 pf 5v 5v v cm 10 ? 10 nf 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e 0. 1 f sco pe 30 v 43 0 ? 2. 1k ? 0. 1 f 15 pf 5v v cm 10 nf 10 nf 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e 0. 1 f 0. 1 f sco pe 30 v 0. 1 f 0. 1 f 15 pf 15 pf 5v 5v figure 30. t desat fault test circuit 10 nf + _ 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e + _ 5v 0. 1 f 0. 1 f v ou t 30 v 10 ? v in 2. 1k ? v f aul t 10 ma 10 nf + _ 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 v s ca th od e ano de ano de ca th od e + _ 5v 0. 1 f 0. 1 f 0. 1 f 0. 1 f v ou t 30 v v in v f aul t 10 ma 10 ma figure 31. cmr test circuit led2 of figure 32. cmr test circuit led2 on
18 figure 33. cmr test circuit led1 of 10 10 nf 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e 0. 1 f sco pe 30 v v cm 43 0 ? 2. 1k ? 0. 1 f 15 pf 5v 10 10 ? 10 nf 10 nf 0. 1 f 0. 1 f sco pe 30 v figure 34. cmr test circuit led1 on v cm 10 10 nf 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e 0. 1 f sco pe 30 v 43 0 2. 1k 0. 1 f 15 pf 5v sco pe 2. 1k ? 0. 1 f 15 pf 5v ? ?
19 application information product overview description the acpl-332j is a highly integrated power control device that incorporates all the necessary components for a complete, isolated igbt / mosfet gate drive circuit with fault protection and feedback into one so-16 package. active miller clamp function eliminates the need of negative gate drive in most application and allows the use of simple bootstrap supply for high side driver. an optically isolated power output stage drives igbts with power ratings of up to 150 a and 1200 v. a high speed internal optical link minimizes the propagation delays between the microcontroller and the igbt while allowing the two systems to operate at very large common mode voltage diferences that are common in industrial motor drives and other power switching applications. an output ic provides local protection for the igbt to prevent damage during over current, and a second optical link provides a fully isolated fault status feedback signal for the microcontroller. a built in watchdog circuit, uvlo monitors the power stage supply voltage to prevent igbt caused by insufcient gate drive voltages. this integrated igbt gate driver is designed to increase the performance and reliability of a motor drive without the cost, size, and complexity of a discrete design. two light emitting diodes and two integrated circuits housed in the same so-16 package provide the input control circuitry, the output power stage, and two optical channels. the output detector ic is designed manufac - tured on a high voltage bicmos/power dmos process. the forward optical signal path, as indicated by led1, transmits the gate control signal. the return optical signal path, as indicated by led2, transmits the fault status feedback signal. under normal operation, the led1 directly controls the igbt gate through the isolated output detector ic, and led2 remains of. when an igbt fault is detected, the output detector ic immediately begins a soft shutdown sequence, reducing the igbt current to zero in a con - trolled manner to avoid potential igbt damage from inductive over voltages. simultaneously, this fault status is transmitted back to the input via led2, where the fault latch disables the gate control input and the active low fault output alerts the microcontroller. during power-up, the under voltage lockout (uvlo) feature prevents the application of insufcient gate voltage to the igbt, by forcing the acpl-332js output low. once the output is in the high state, the desat (vce) detection feature of the acpl-332j provides igbt pro - tection. thus, uvlo and desat work in conjunction to provide constant igbt protection. recommended application circuit the acpl-332j has an led input gate control, and an open collector fault output suitable for wired or ap - plications. the recommended application circuit shown in figure 36 illustrates a typical gate drive implementa - tion using the acpl-332j. the following describes about driving igbt. however, it is also applicable to mosfet. depending upon the mosfet or igbt gate threshold re - quirements, designers may want to adjust the vcc supply voltage (recommended v cc = 17.5v for igbt and 12.5v for mosfet). the two supply bypass capacitors (0.1 f) provide the large transient currents necessary during a switching transition. because of the transient nature of the charging currents, a low current (5ma) power supply sufces. the desaturation diode d desat 600v/1200v fast recovery type, t rr below 75ns (e.g. era34-10) and capacitor c blank are necessary external components for the fault detection circuitry. the gate resistor r g serves to limit gate charge current and controls the igbt collector voltage rise and fall times. the open collector fault output has a passive pull-up resistor r f (2.1 k w ) and a 330 pf fltering capacitor, c f . a 47 k w pull down resistor r pull-down on v out provides a predictable high level output voltage (v oh ). in this application, the igbt gate driver will shut down when a fault is detected and fault reset by next cycle of igbt turn on. application notes are mentioned at the end of this datasheet. figure 35. block diagram of acpl-332j shi el d shi el d d r i v e r v e de sa t v cc2 v ou t v cl am p v ee v cc1 v s fa ul t ano de ca th od e v cl am p v le d 6, 7 5, 8 2 3 1, 4 13 11 14 9, 1 2 10 16 15 de sa t uv lo le d1 le d2 shi el d shi el d d r i v e r v e de sa t v cc2 v ou t v cl am p v ee v cc1 v s fa ul t ano de ca th od e v cl am p v le d 6, 7 5, 8 2 3 1, 4 13 11 14 9, 1 2 10 16 15 de sa t uv lo le d1 le d2
20 description of operation normal operation during normal operation, v out of the acpl-332j is con - trolled by input led current if (pins 5, 6, 7 and 8), with the igbt collector-to-emitter voltage being monitored through ddesat. the fault output is high. see figure 37. fault condition the desat pin monitors the igbt v ce voltage. when the voltage on the desat pin exceeds 6.5 v while the igbt is on, v out is slowly brought low in order to softly turn-of the igbt and prevent large di/dt induced voltages. also figure 37. fault timing diagram figure 36. recommended application circuit (single supply) with desaturation detection and active miller clamp activated is an internal feedback channel which brings the fault output low for the purpose of notifying the micro-controller of the fault condition. fault reset once fault is detected, the output will be muted for 5 s (minimum). all input led signals will be ignored during the mute period to allow the driver to completely soft shut-down the igbt. the fault mechanism can be reset by the next led turn-on after the 5us (minimum) mute time. see figure 37. + _ + _ 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v led desat v cc2 v ee v out v clamp v ee v s v cc1 fault v s cathod e anod e anod e cathod e + _ r g 100 ? c blank d desat q1 q2 + v ce - r f r r pull - down + hvdc - h vd c 3- phase ac + v ce - 0.1 f 0.1 f 0.1 f c f 7 + _ - i f v d e s a t v o u t f a u l t 6 . 5 v 5 0 % t d e s a t ( l o w ) 1 0 % t d e s a t ( 1 0 % ) 9 0 % t d e s a t ( 9 0 % ) 5 0 % t d e s a t ( f a u l t ) t d e s a t ( m u t e ) ) 5 0 % t r e s e t ( f a u l t ) r e s e t d o n e d u r i n g t h e n e x t l e d t u r n - o n ) ) ) ) ) t b l a n k
21 output control the outputs (v out and fault) of the acpl-332j are con - trolled by the combination of i f , uvlo and a detected igbt desat condition. once uvlo is not active (v cc2 - v e > v uvlo ), vout is allowed to go high, and the desat (pin 14) detection feature of the acpl-332j will be the primary source of igbt protection. uvlo is needed to ensure desat is functional. once v uvlo+ > 10.5 v, desat will remain functional until v uvlo- < 11.1 v. thus, the desat detection and uvlo features of the acpl-332j work in conjunction to ensure constant igbt protection. desaturation detection and high current protection the acpl-332j satisfes these criteria by combining a high speed, high output current driver, high voltage optical isolation between the input and output, local igbt de - saturation detection and shut down, and an optically isolated fault status feedback signal into a single 16-pin surface mount package. the fault detection method, which is adopted in the acpl-332j, is to monitor the saturation (collector) voltage of the igbt and to trigger a local fault shutdown sequence if the collector voltage exceeds a predeter - mined threshold. a small gate discharge device slowly reduces the high short circuit igbt current to prevent damaging voltage spikes. before the dissipated energy can reach destructive levels, the igbt is shut of. during the of state of the igbt, the fault detect circuitry is simply disabled to prevent false fault signals. the alternative protection scheme of measuring igbt current to prevent desaturation is efective if the short circuit capability of the power device is known, but this method will fail if the gate drive voltage decreases enough to only partially turn on the igbt. by directly measuring the collector voltage, the acpl-332j limits the power dissipation in the igbt even with insufcient gate drive voltage. another more subtle advantage of the de - saturation detection method is that power dissipation in the igbt is monitored, while the current sense method relies on a preset current threshold to predict the safe limit of operation. therefore, an overly conservative over current threshold is not needed to protect the igbt. i f uvlo (v cc2 C v e ) desat condition detected on pin 14 pin 3 (fault) output v out x active x x low x x yes low low off x x x low on not active no high high slow igbt gate discharge during fault condition when a desaturation fault is detected, a weak pull-down device in the acpl-332j output drive stage will turn on to softly turn of the igbt. this device slowly discharges the igbt gate to prevent fast changes in drain current that could cause damaging voltage spikes due to lead and wire inductance. during the slow turn of, the large output pull-down device remains of until the output voltage falls below v ee + 2 volts, at which time the large pull down device clamps the igbt gate to v ee . desat fault detection blanking time the desat fault detection circuitry must remain disabled for a short time period following the turn-on of the igbt to allow the collector voltage to fall below the desat threshold. this time period, called the desat blanking time is controlled by the internal desat charge current, the desat voltage threshold, and the external desat capacitor. the nominal blanking time is calculated in terms of external capacitance (c blank ), fault threshold voltage (v desat ), and desat charge current (i chg ) as t blank = c blank x v desat / i chg . the nominal blanking time with the recommended 100pf capacitor is 100pf * 6.5 v / 240 a = 2.7 sec. the capacitance value can be scaled slightly to adjust the blanking time, though a value smaller than 100 pf is not recommended. this nominal blanking time represents the longest time it will take for the acpl-332j to respond to a desat fault condition. if the igbt is turned on while the collector and emitter are shorted to the supply rails (switching into a short), the soft shut-down sequence will begin after approximately 3 sec. if the igbt collector and emitter are shorted to the supply rails after the igbt is already on, the response time will be much quicker due to the parasitic parallel capacitance of the desat diode. the recommended 100pf capacitor should provide adequate blanking as well as fault response times for most applications.
22 figure 38. output pull-down resistor. under voltage lockout the acpl-332j under voltage lockout (uvlo) feature is designed to prevent the application of insufcient gate voltage to the igbt by forcing the acpl-332j output low during power-up. igbts typically require gate voltages of 15 v to achieve their rated v ce(on) voltage. at gate voltages below 13 v typically, the v ce(on) voltage increases dramatically, especially at higher currents. at very low gate voltages (below 10 v), the igbt may operate in the linear region and quickly overheat. the uvlo function causes the output to be clamped whenever in - sufcient operating supply (v cc2 ) is applied. once v cc2 exceeds v uvlo+ (the positive-going uvlo threshold), the uvlo clamp is released to allow the device output to turn on in response to input signals. as v cc2 is increased from 0 v (at some level below v uvlo+ ), frst the desat protec - tion circuitry becomes active. as v cc2 is further increased (above v uvlo+ ), the uvlo clamp is released. before the time the uvlo clamp is released, the desat protection is already active. therefore, the uvlo and desat fault detection feature work together to provide seamless pro - tection regardless of supply voltage (v cc2 ). active miller clamp a miller clamp allows the control of the miller current during a high dv/dt situation and can eliminate the use of a negative supply voltage in most of the applications. during turn-of, the gate voltage is monitored and the clamp output is activated when gate voltage goes below 2v (relative to v ee ). the clamp voltage is v ol +2.5v typ for a miller current up to 1100ma. the clamp is disabled when the led input is triggered again. other recommended components the application circuit in figure 36 includes an output pull-down resistor, a desat pin protection resistor, a fault pin capacitor, and a fault pin pullup resistor and active miller clamp connection. output pull-down resistor during the output high transition, the output voltage rapidly rises to within 3 diode drops of v cc2 . if the output current then drops to zero due to a capacitive load, the output voltage will slowly rise from roughly v cc2 -3(v be ) to v cc2 within a period of several microseconds. to limit the output voltage to v cc2 -3(v be ), a pull-down resistor, r pull-down between the output and v ee is recommended to sink a static current of several 650 a while the output is high. pull-down resistor values are dependent on the amount of positive supply and can be adjusted according to the formula, r pull-down = [v cc2 -3 * (v be )] / 650 a. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e r g r pull -d ow n v cc 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e r g r pull -d ow n v cc desat pin protection resistor the freewheeling of fyback diodes connected across the igbts can have large instantaneous forward voltage transients which greatly exceed the nominal forward voltage of the diode. this may result in a large negative voltage spike on the desat pin which will draw substan - tial current out of the driver if protection is not used. to limit this current to levels that will not damage the driver ic, a 100 ohm resistor should be inserted in series with the desat diode. the added resistance will not alter the desat threshold or the desat blanking time. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v le d de sa t v cc2 v ee v ou t v cl am p v ee v s v cc1 fa ul t v s ca th od e ano de ano de ca th od e r g v cc 100 ? 10 0pf d desa t figure 39. desat pin protection. capacitor on fault pin for high cmr rapid common mode transients can afect the fault pin voltage while the fault output is in the high state. a 330 pf capacitor should be connected between the fault pin and ground to achieve adequate cmos noise margins at the specifed cmr value of 15 kv/s. the added capaci - tance does not increase the fault output delay when a desaturation condition is detected.
23 figure 41. large igbt drive with negative gate drive, external booster. v clamp control secondary discharge path for higher power application. figure 40. igbt drive with negative gate drive, external booster and desaturation detection (v clamp should be connected to v ee when it is not used) vclamp is used as secondary gate discharge path. * indicates component required for negative gate drive topology pull-up resistor on fault pin the fault pin is an open collector output and therefore requires a pull-up resistor to provide a high-level signal. also the fault output can be wire ored together with other types of protection (e.g. over-temperature, over- voltage, over-current ) to alert the microcontroller. other possible application circuit (output stage) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v led desat v cc2 v ee v out v clamp v ee v s v cc1 fault v s cathode anode anode cathode + _ + _ r g q1 q2 + v ce - r pull- dow n + hvdc - hvdc 3- phase ac + v ce - 0.1 f 0.1 f 0.1 f optional r 1 optional r 2 r g optional r 1 optional r 2 * 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v e v led desat v cc2 v ee v out v clamp v ee v s v cc1 fault v s cathode anode anode cathode + _ + _ r g q1 q2 + v ce - r pull- dow n + hvdc - hvdc 3- phase ac + v ce - 0.1 f 0.1 f 0.1 f optional r 1 optional r 2 r 3 9 r g optional r 1 optional r 2 r 3 *
related application notes an5314 C active miller clamp an5324 - desaturation fault detection an5315 C soft turn-of feature an1087 C thermal data for optocouplers an1043 C common-mode noise : sources and solutions an02-0310en - plastics optocoupler product esd and moisture sensitivity for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2008 avago technologies. all rights reserved. av02-0120en - november 6, 2008

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